This application claims the benefit of Korean Patent Application No. 2002-0042573, filed Jul. 19, 2002, the disclosure of which is hereby incorporated herein by reference in its entirety as if set forth fully herein.
The present invention relates to integrated circuit capacitors, and more particularly to Metal-Insulator-Metal (MIM) integrated circuit capacitors.
Since integrated circuit capacitors are used in a variety of integrated circuit devices, integrated circuit capacitors having relatively high speed and/or relatively large capacitance may be desired. As is well known to those having skill in the art, an integrated circuit capacitor includes first (lower) and second (upper) electrodes on an integrated circuit substrate, with a capacitor dielectric therebetween. In general, in order to realize capacitors having high speed, frequency dependence may be decreased by reducing the resistance of the capacitor electrodes. In addition, in order to realize capacitors of relatively large capacitance, the thickness of a dielectric layer between capacitor electrodes may be reduced, a high dielectric material may be used for the dielectric layer, and/or the area of the electrodes may be increased.
Capacitors used in integrated circuit devices may be classified into capacitors having a Metal-Oxide-Semiconductor (MOS) structure, capacitors having a pn junction structure, capacitors having a Polysilicon-Insulator-Polysilicon (PIP) structure, and capacitors having a Metal-Insulator-Metal (MIM) structure. Monocrystalline silicon or polycrystalline silicon may be used as at least one electrode material in capacitors of all of the above structures except the MIM structure. However, due to the physical properties of monocrystalline silicon or polycrystalline silicon, there may be limitations in reducing the resistance of the capacitor electrode. Hence, a MIM capacitor, which can provide metal capacitor electrodes having low resistance, may be used in applications that desire high-speed capacitor applications.
FIG. 1A shows a conventional MIM capacitor. FIG. 1B shows an equivalent circuit diagram of the MIM capacitor of FIG. 1A.
Referring to FIG. 1A, a MIM capacitor 10 includes a lower metal layer 11, a dielectric layer 12, and an upper metal layer 13. The dielectric layer 12 is arranged between the lower metal layer 11 and the upper metal layer 13. In general, the upper metal layer 13 may be connected to a power terminal for supplying a voltage V having a predetermined level, and the lower metal layer 11 may be grounded (connected to a ground terminal). The MIM capacitor 10 has a predetermined capacitance C, as shown in FIG. 1B. Ideally, the capacitance C should be a constant value regardless of variation in the voltage V.
FIG. 2 shows a graph illustrating voltage-capacitance characteristics of a MIM capacitor of FIG. 1A. As shown in FIG. 2, in practice, the capacitance C of the conventional MIM capacitor 10 may vary as the voltage V is varied. The variation may be classified into two cases: a case (21) where the capacitance C is increased as the voltage V is increased, and a case (22) where the capacitance C is decreased as the voltage V is increased.
Whether the capacitance C is increased or decreased as the voltage V is increased may depend on the material used to form the dielectric layer 12. For example, when the dielectric layer 12 of the MIM capacitor 10 is formed of silicon nitride (SixNy), the capacitance C may decrease as the voltage V is increased. In any event, this real-world variation in capacitance as a function of voltage can negatively impact the performance of an integrated circuit device in which the MIM capacitor is used.
Metal-insulator-metal integrated circuit capacitors according to some embodiments of the present invention include a pair of metal-insulator-metal capacitors on an integrated circuit substrate that are electrically connected in antiparallel. In some embodiments, the pair of metal-insulator-metal capacitors comprise first and second portions of a first metal layer on an integrated circuit substrate, first and second portions of an insulating layer, a respective one of which is on a respective one of the first and second portions of the first metal layer, opposite the integrated circuit substrate, and first and second portions of a second metal layer, a respective one of which is on a respective one of the first and second portions of the insulating layer, opposite the first and second portions of the first metal layer. The first portion of the first metal layer is electrically connected to the second portion of the second metal layer, and the second portion of the first metal layer is electrically connected to the first portion of the second metal layer. In other embodiments, the pair of metal-insulator-metal capacitors has less capacitance variation as a function of voltage than either of the metal-insulator-metal capacitors.
According to other embodiments of the present invention, a metal-insulator-metal capacitor includes a first capacitor, in which a first lower metal layer, a first dielectric layer, and a first upper metal layer are stacked in sequence on an integrated circuit substrate. A second capacitor, in which a second lower metal layer, a second dielectric layer, and a second upper metal layer are stacked in sequence on the integrated circuit substrate, is also provided. The second lower metal layer is electrically connected to the first upper metal layer and the second upper metal layer is electrically connected to the first lower metal layer.
In some embodiments, the first upper metal layer of the first capacitor and the second lower metal layer of the second capacitor are connected to a power terminal, and the first lower metal layer of the first capacitor and the second upper metal layer of the second capacitor are connected to a ground terminal. In some embodiments, the first dielectric layer includes an SiO2 layer, SixNy layer, SixOyFz layer, SixOyNz layer, and/or SixOyHz layer. In other embodiments, the second dielectric layer includes an SiO2 layer, SixNy layer, SixOyFz layer, SixOyNz layer and/or SixOyHz layer.
Metal-insulator-metal integrated circuit capacitor structures according to other embodiments of the invention include a first dielectric layer-on an integrated circuit substrate and first and second spaced apart portions of a first metal layer in the first dielectric layer. A second dielectric layer is provided on the first dielectric layer. First and second spaced apart portions of a capacitor dielectric layer are provided in the second dielectric layer, a respective one of which is on a respective one of the first and second spaced apart portions of the first metal layer. First and second spaced apart portions of a second dielectric layer also are provided, a respective one of which is on a respective one of the first and second spaced apart portions of the capacitor dielectric layer. In some embodiments, a first conductive contact electrically connects the first portion of the first metal layer to the second portion of the second metal layer, through the second dielectric layer. In other embodiments, a second conductive contact electrically contacts the second portion of the first metal layer to the first portion of the second metal layer, through the second dielectric layer. In still other embodiments, a third conductive contact electrically connects the second portion of the second metal layer to the integrated circuit substrate through the first and second dielectric layers. In still other embodiments, a fourth conductive contact electrically contacts the second portion of the first metal layer to the integrated circuit substrate.
According to other embodiments of the present invention, an integrated circuit device includes an integrated circuit substrate, a first interlayer dielectric (ILD) layer on the integrated circuit substrate and a first lower metal layer and a second lower metal layer on a first level on the surface of the first ILD layer, separated from each other by a second ILD layer. A first dielectric layer is on the first lower metal layer and a second dielectric layer is on the second lower metal layer. A third dielectric layer separates the first dielectric layer and the second dielectric layer from each other. A first upper metal layer and a second upper metal layer are also provided, a respective one of which is on a respective one of the first dielectric layer and the second dielectric layer, while being separated from each other on a second level on surfaces of the first dielectric layer and the second dielectric layer.
In some embodiments, the first dielectric layer includes an SiO2 layer, SixNy layer, SixOyFz layer, SixOyNz layer, and/or SixOyHz layer. In other embodiments, the second dielectric layer includes an SiO2 layer, SixNy layer, SixOyFz layer, SixOyNz layer, and/or SixOyHz layer.
In some embodiments, the integrated circuit device further includes a first conductive contact penetrating the first ILD layer, the second ILD layer, and the third ILD layer and connecting an active region of the integrated circuit substrate to the second upper metal layer. In other embodiments, the integrated circuit device further includes a second conductive contact penetrating the first ILD layer and connecting an active region of the integrated circuit substrate to the second lower metal layer. In yet other embodiments, the integrated circuit device further includes a third conductive contact penetrating the third ILD layer and connecting the second upper metal layer to the first lower metal layer. In still other embodiments, the integrated circuit device farther includes a fourth conductive contact penetrating the third ILD layer and connecting the first upper metal layer to the second lower metal layer.